Intel Nehalem (microarchitecture) - Revision history

Onnowpurbo: /* Successor */

2010-02-10T01:17:14Z

Successor

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	[[Image:IntelProcessorRoadmap.jpg\|500px\|center\|thumb\|Intel CPU core roadmaps from ''[[Intel NetBurst\|NetBurst]]'' to ''[[Intel Sandy Bridge (microarchitecture)\|Sandy Bridge]]'']]		[[Image:IntelProcessorRoadmap.jpg\|500px\|center\|thumb\|Intel CPU core roadmaps from ''[[Intel NetBurst\|NetBurst]]'' to ''[[Intel Sandy Bridge (microarchitecture)\|Sandy Bridge]]'']]


			==See Also==
			* [[Intel Core i7\|Core i7]]
			* [[X86]] instruction set architecture
			* [[x86-64]]
			* [[Xeon]]
			* [[Pentium]]
			* [[Intel P6 (microarchitecture)\|P6]]
			* [[Intel NetBurst (microarchitecture)\|NetBurst]]
			* [[Intel Core (microarchitecture)\|Core]]
			* [[Intel Sandy Bridge (microarchitecture)\|Sandy Bridge]]
			* [[Intel Haswell (microarchitecture)\|Haswell]]
			* [[List of Intel CPU microarchitectures]]

			==External links==

			*[http://www.intel.com/technology/architecture-silicon/next-gen/ Nehalem processor] at [[Intel]].com

Onnowpurbo: /* Westmere */

2010-02-10T01:16:44Z

Westmere

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	* Improved virtualization latency.		* Improved virtualization latency.
	* New virtualization capability: "VMX Unrestricted mode support," which allows 16-bit guests to run (real mode and big real mode).		* New virtualization capability: "VMX Unrestricted mode support," which allows 16-bit guests to run (real mode and big real mode).



			==Successor==

			The successor to ''Nehalem'' and ''Westmere'' will be ''[[Intel Sandy Bridge (microarchitecture)\|Sandy Bridge]]'', scheduled for release in 2011, according to Intel roadmaps. The successor to ''Sandy Bridge'' will be ''[[Intel Haswell (microarchitecture)\|Haswell]]'', scheduled for release in 2012. It will come with a new cache subsystem, a FMA ([[Multiply-accumulate\|fused multiply-add]]) unit, and a vector coprocessor.

			[[Image:IntelProcessorRoadmap.jpg\|500px\|center\|thumb\|Intel CPU core roadmaps from ''[[Intel NetBurst\|NetBurst]]'' to ''[[Intel Sandy Bridge (microarchitecture)\|Sandy Bridge]]'']]

Onnowpurbo at 01:16, 10 February 2010

2010-02-10T01:16:20Z

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	''Clarkdale'' and ''Arrandale'' contain the 32 nm dual core processor ''Hillel'' and the 45 nm integrated graphics device ''Ironlake'', and support switchable graphics. The lowest-power variant of Arrandale may have a 10 W CPU TDP, and a maximum clock speed of 1.6 GHz.		''Clarkdale'' and ''Arrandale'' contain the 32 nm dual core processor ''Hillel'' and the 45 nm integrated graphics device ''Ironlake'', and support switchable graphics. The lowest-power variant of Arrandale may have a 10 W CPU TDP, and a maximum clock speed of 1.6 GHz.
	A successor to ''Bloomfield'' and entry level server chips are also expected in Q2 2010.		A successor to ''Bloomfield'' and entry level server chips are also expected in Q2 2010.


			====Westmere====
			'''Westmere''' (formerly '''Nehalem-C''') is the name given to the [[32 nanometer\|32 nm]] [[die shrink]] of ''Nehalem''. ''Westmere'' was to be ready for a Q4 2009 release provided that Intel stayed on target with their roadmap. However, the first Westmere-based processors were launched on January 7, 2010 as the Core i3, Core i5, and dual-core mobile Core i7.

			Westmere's features and improvements from Nehalem have been reported as follows:

			* Native six-core, and possibly dual-die hex-core (12-cores), processors.
			** The successor to Bloomfield and Gainestown is six-core.
			* A new set of instructions that gives over 3x the encryption and decryption rate of [[Advanced Encryption Standard]] (AES) processes compared to before.
			** Delivers seven new instructions ([[AES instruction set]] or [[AES-NI]]) that will be used by the AES algorithm. Also an instruction called PCLMULQDQ (see [[CLMUL instruction set]]) that will perform carry-less multiplication for use in cryptography. These instructions will allow the processor to perform hardware-accelerated encryption, not only resulting in faster execution but also protecting against software targeted attacks.
			** AES-NI may be included in the integrated graphics of Westmere.
			* Integrated graphics, released at the same time as the processor.
			* Improved virtualization latency.
			* New virtualization capability: "VMX Unrestricted mode support," which allows 16-bit guests to run (real mode and big real mode).

Onnowpurbo at 01:15, 10 February 2010

2010-02-10T01:15:50Z

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	\|		\|
	\|}		\|}


			For the desktop, ''Gulftown'' is to be an "Extreme Edition" CPU and so will coexist with ''Bloomfield.'' It will have Turbo Boost and similar clock speeds to Bloomfield.

			''Lynnfield'' and ''Clarksfield'' may make the 32 nm transition in the middle of 2010, sometime after Q2, while ''Beckton'' will move to 32 nm at the end of 2010.
			The 32 nm CPUs will not have significantly different clock speeds compared to 45 nm CPUs.
			''Clarkdale'' and ''Arrandale'' contain the 32 nm dual core processor ''Hillel'' and the 45 nm integrated graphics device ''Ironlake'', and support switchable graphics. The lowest-power variant of Arrandale may have a 10 W CPU TDP, and a maximum clock speed of 1.6 GHz.
			A successor to ''Bloomfield'' and entry level server chips are also expected in Q2 2010.

Onnowpurbo: /* 45 nm processors */

2010-02-10T01:14:40Z

45 nm processors

Show changes

Onnowpurbo: /* 45 nm processors */

2010-02-10T01:14:06Z

45 nm processors

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	\|-		\|-
	! rowspan=2 \| Codename		! rowspan=2 \| Codename
			! rowspan=2 \| Market
			! rowspan=2 \| [[Multi-core\|Cores]]<br />(Threads)
			! rowspan=2 \| [[CPU socket\|Socket]]
			! rowspan=2 \| Brand
			! rowspan=2 \| Processor No.
			! colspan=3 \| [[Clock rate]]
			! rowspan=2 \| Turbo
			! rowspan=2 \| [[Thermal Design Power\|TDP]]
			! colspan=3 \| Interfaces
			! rowspan=2 \| [[CPU_cache#Multi-level_caches\|L3 cache]]
			! rowspan=2 \| Release
			! rowspan=2 \| 1k Unit Price
			\|-

Onnowpurbo: /* Variants */

2010-02-10T01:13:45Z

Variants

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	* "Extreme" processors have an [[CPU locking\|unlocked]] [[CPU multiplier\|clock multiplier]]. [[Thermal design power]] (TDP) values for CPUs with integrated GPUs include the GPU.		* "Extreme" processors have an [[CPU locking\|unlocked]] [[CPU multiplier\|clock multiplier]]. [[Thermal design power]] (TDP) values for CPUs with integrated GPUs include the GPU.
	* All variants have 64 [[Kibibyte\|KiB]] [[CPU_cache#Multi-level_caches\|L1 cache]] per core, and 256 KiB [[CPU_cache#Multi-level_caches\|L2 cache]] per core.		* All variants have 64 [[Kibibyte\|KiB]] [[CPU_cache#Multi-level_caches\|L1 cache]] per core, and 256 KiB [[CPU_cache#Multi-level_caches\|L2 cache]] per core.


			===45 nm processors===
			{\| border="1" cellpadding=2 style="border-collapse: collapse"
			\|-
			! rowspan=2 \| Codename

Onnowpurbo: /* Code names */

2010-02-10T01:13:16Z

Code names

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	\| \|\| \|\| \|\| [[Xeon#Beckton\|Beckton]] 80604		\| \|\| \|\| \|\| [[Xeon#Beckton\|Beckton]] 80604
	\|}		\|}


			==Variants==
			These tables list all the processors of Nehalem microarchitecture to have been leaked so far. The table is ordered roughly by performance, which usually correlates with price and power. Released processors are set in '''bold'''.

			Notes:
			* "Extreme" processors have an [[CPU locking\|unlocked]] [[CPU multiplier\|clock multiplier]]. [[Thermal design power]] (TDP) values for CPUs with integrated GPUs include the GPU.
			* All variants have 64 [[Kibibyte\|KiB]] [[CPU_cache#Multi-level_caches\|L1 cache]] per core, and 256 KiB [[CPU_cache#Multi-level_caches\|L2 cache]] per core.

Onnowpurbo: /* Code names */

2010-02-10T01:12:55Z

Code names

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	Each combination of a Nehalem/Westmere processor die and package has both a separate codename and a product code. Typically, the same dies are used for uniprocessor (UP) and dual-processor (DP) servers, but using an extra QuickPath link for the inter-processor communication in the DP server variant. Where the Core microarchitecture used four different processor sockets, one for each market segment, Nehalem now uses [[Socket 1366]] for the high-end of both UP and DP machines, and [[Socket 1156]] for the low end UP machines. The name for the UP version of Gulftown is not yet known; its product code is 80613 and can be found in Intel's product database		Each combination of a Nehalem/Westmere processor die and package has both a separate codename and a product code. Typically, the same dies are used for uniprocessor (UP) and dual-processor (DP) servers, but using an extra QuickPath link for the inter-processor communication in the DP server variant. Where the Core microarchitecture used four different processor sockets, one for each market segment, Nehalem now uses [[Socket 1366]] for the high-end of both UP and DP machines, and [[Socket 1156]] for the low end UP machines. The name for the UP version of Gulftown is not yet known; its product code is 80613 and can be found in Intel's product database

			{\| border="1" cellpadding=2 style="border-collapse: collapse"
			\|-
			! !! Mobile !! Desktop UP Server !! DP Server !! MP Server
			\|- align="center"
			\| align="left"\|'''Dual-Core 45 nm''' Dual-Channel, PCIe, Graphics Core
			\| Auburndale ''canceled'' \|\| Havendale ''canceled'' \|\| \|\|
			\|- align="center"
			\| align="left"\|'''Dual-Core 32 nm''' Dual-Channel, PCIe, Graphics Core
			\| [[Arrandale (microprocessor)\|Arrandale]] 80617 \|\| [[Clarkdale (microprocessor)\|Clarkdale]] 80616 \|\| \|\|
			\|- align="center"
			\| align="left"\|'''Quad-Core 45 nm''' Dual-Channel, PCIe
			\| [[Clarksfield (microprocessor)\|Clarksfield]] 80607 \|\| [[Lynnfield (microprocessor)\|Lynnfield]] 80605 \|\| [[Xeon#Jasper Forest\|Jasper Forest]] 80612 \|\|
			\|- align="center"
			\| align="left"\|'''Quad-Core 45 nm''' Triple-Channel
			\| \|\| [[Bloomfield (microprocessor)\|Bloomfield]] 80601 \|\| [[Xeon#5500-series "Gainestown"\|Gainestown]] 80602 \|\|
			\|- align="center"
			\| align="left"\|'''Six-Core 32 nm''' Triple-Channel
			\| \|\| [[Gulftown (microprocessor)\|Gulftown]] 80613 \|\| [[Gulftown (microprocessor)\|Gulftown]] 80614 \|\|
			\|- align="center"
			\| align="left"\|'''Eight-Core 45 nm''' Triple-Channel
			\| \|\| \|\| \|\| [[Xeon#Beckton\|Beckton]] 80604
			\|}

Onnowpurbo: /* Performance and power improvements */

2010-02-10T01:12:16Z

Performance and power improvements

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	The Nehalem processors are the first to incorporate the [[SSE4#SSE4.2\|SSE 4.2]] SIMD instructions, adding 7 new instructions to the SSE 4.1 set available in the Core 2 series.		The Nehalem processors are the first to incorporate the [[SSE4#SSE4.2\|SSE 4.2]] SIMD instructions, adding 7 new instructions to the SSE 4.1 set available in the Core 2 series.

			== Code names ==

			Each combination of a Nehalem/Westmere processor die and package has both a separate codename and a product code. Typically, the same dies are used for uniprocessor (UP) and dual-processor (DP) servers, but using an extra QuickPath link for the inter-processor communication in the DP server variant. Where the Core microarchitecture used four different processor sockets, one for each market segment, Nehalem now uses [[Socket 1366]] for the high-end of both UP and DP machines, and [[Socket 1156]] for the low end UP machines. The name for the UP version of Gulftown is not yet known; its product code is 80613 and can be found in Intel's product database

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	\|-		\|-
	! rowspan=2 \| Codename		! rowspan=2 \| Codename
			! rowspan=2 \| Market
			! rowspan=2 \| [[Multi-core\|Cores]]<br />(Threads)
			! rowspan=2 \| [[CPU socket\|Socket]]
			! rowspan=2 \| Brand
			! rowspan=2 \| Processor No.
			! colspan=3 \| [[Clock rate]]
			! rowspan=2 \| Turbo
			! rowspan=2 \| [[Thermal Design Power\|TDP]]
			! colspan=3 \| Interfaces
			! rowspan=2 \| [[CPU_cache#Multi-level_caches\|L3 cache]]
			! rowspan=2 \| Release
			! rowspan=2 \| 1k Unit Price
			\|-