Onnowpurbo: New page: The acronym '''RISC''' (pronounced as ''risk''), for '''reduced instruction set computer''', represents a CPU design strategy emphasizing the insight that simplifie...

2010-01-14T22:35:03Z

New page: The acronym '''RISC''' (pronounced as ''risk''), for '''reduced instruction set computer''', represents a CPU design strategy emphasizing the insight that simplifie...

New page

The acronym '''RISC''' (pronounced as ''[[wiktionary:risk|risk]]''), for '''reduced instruction set computer''', represents a [[CPU design]] strategy emphasizing the insight that simplified instructions that "do less" may still provide for higher performance if this simplicity can be utilized to make instructions execute very quickly. Many proposals for a "precise" definition have been attempted, and the term is being slowly replaced by the more descriptive '''load-store architecture'''. Well known RISC families include [[DEC Alpha|Alpha]], [[AMD 29k|Am29k]], [[ARC International|ARC]], [[ARM architecture|ARM]], [[Atmel AVR|AVR]], [[MIPS architecture|MIPS]], [[PA-RISC]], [[Power Architecture]] (including [[PowerPC]]), [[SuperH]], and [[SPARC]].

Being an old idea, some aspects attributed to the first RISC-''labeled'' designs (around 1975) include the observations that the memory restricted [[compiler]]s of the time were often unable to take advantage of features intended to facilitate manual assembly coding, and that complex [[addressing mode|addressing]] ''inherently'' takes many cycles to perform, due to the implied additional memory accesses. It was argued that such functions would better be performed by sequences of simpler instructions, if this could yield implementations simple enough to cope with really high [[clock frequency|frequencies]], and small enough to leave room for many registers, factoring out slow memory accesses. Uniform, fixed length instructions with arithmetics restricted to registers were chosen to ease [[instruction pipeline|instruction pipelining]] in these simple designs, with special ''load-store'' instructions accessing memory.

==Non-RISC design philosophy==


In the early days of the computer industry, programming was done in [[assembly language]] or [[machine code]], which encouraged powerful and easy to use instructions. CPU designers therefore tried to make instructions that would do as much work as possible. With the advent of [[high level language|higher level language]]s, computer architects also started to create dedicated instructions to directly implement certain central mechanisms of such languages. Another general goal was to provide every possible [[addressing mode]] for every instruction, known as [[Orthogonality#Computer_science|orthogonality]], to ease compiler implementation. Arithmetic operations could therefore often have results as well as operands directly in memory (in addition to register or immediate).

The attitude at the time was that hardware design was more mature than [[compiler design]] so this was in itself also a reason to implement parts of the functionality in hardware and/or [[microcode]] rather than in a memory constrained compiler (or its generated code) alone. This design philosophy became retroactively termed [[Complex Instruction Set Computer]] (CISC) after the RISC philosophy came onto the scene.

CPUs also had relatively few registers, for several reasons:
* More registers also implies more time-consuming saving and restoring of register contents on the machine stack.
* A large number of registers requires a large number of instruction bits as register specifiers, meaning less dense code (see below).
* CPU registers are more expensive than external memory locations; large register sets were cumbersome with limited [[Printed circuit board|circuit boards]] or chip integration.

An important force encouraging complexity was very limited main memories (on the order of kilobytes). It was therefore advantageous for the density of information held in computer programs to be high, leading to features such as highly encoded, variable length instructions, doing data loading as well as calculation (as mentioned above). These issues were of higher priority than the ease of decoding such instructions.

An equally important reason was that main memories were quite slow (a common type was ferrite [[core memory]]); by using dense information packing, one could reduce the frequency with which the CPU had to access this slow resource. Modern computers face similar limiting factors: main memories are slow compared to the CPU and the fast cache memories employed to overcome this are instead limited in size. This may partly explain why highly encoded instruction sets have proven to be as useful as RISC designs in modern computers.

==RISC design philosophy==
In the mid 1970s researchers (particularly [[John Cocke]]) at [[IBM]] (and similar projects elsewhere) demonstrated that the majority of combinations of these orthogonal [[addressing mode]]s and instructions were not used by most programs generated by [[compiler]]s available at the time. It proved difficult in many cases to write a compiler with more than limited ability to take advantage of the features provided by conventional CPUs.

It was also discovered that, on microcoded implementations of certain architectures, complex operations tended to be ''slower'' than a sequence of simpler operations doing the same thing. This was in part an effect of the fact that many designs were rushed, with little time to optimize or tune every instruction, but only those used most often. One infamous example was the [[VAX]]'s <code>INDEX</code> instruction, which ran slower than an equivalent implementation using simpler operations.

As mentioned elsewhere, core memory had long since been slower than many CPU designs. The advent of semiconductor memory reduced this difference, but it was still apparent that more [[processor register|registers]] (and later [[cache]]s) would allow higher CPU operating frequencies. Additional registers would require sizeable chip or board areas which, at the time (1975), could be made available if the complexity of the CPU logic was reduced.

Yet another impetus of both RISC and other designs came from practical measurements on real-world programs. [[Andrew S. Tanenbaum|Andrew Tanenbaum]] summed up many of these, demonstrating that processors often had oversized immediates. For instance, he showed that 98% of all the constants in a program would fit in 13 [[bit]]s, yet many CPU designs dedicated 16 or 32 bits to store them. This suggests that, to reduce the number of memory accesses, a fixed length machine could store constants in unused bits of the instruction word itself, so that they would be immediately ready when the CPU needs them (much like immediate addressing in a conventional design). This required small [[opcode]]s in order to leave room for a reasonably sized constant in a 32-bit instruction word.

Since many real-world programs spend most of their time executing simple operations, some researchers decided to focus on making those operations as fast as possible. The [[clock rate]] of a CPU is limited by the time it takes to execute the slowest ''sub-operation'' of any instruction; decreasing that cycle-time often accelerates the execution of other instructions.

The focus on "reduced instructions" led to the resulting machine being called a "reduced instruction set computer" (RISC). The goal was to make instructions so simple that they could ''easily'' be [[pipeline (computing)|pipelined]], in order to achieve a ''single clock'' throughput at ''high frequencies''.

Later it was noted that one of the most significant characteristics of
RISC processors was that external memory was only accessible by a
''load'' or ''store'' instruction. All other instructions were limited
to internal registers. This simplified many aspects of processor
design: allowing instructions to be fixed-length, simplifying pipelines,
and isolating the logic for dealing with the delay in completing a memory
access (cache miss, etc) to only two instructions. This led to RISC designs being referred to as ''load/store''
architectures.

== Instruction set size and alternative terminology ==

A common misunderstanding of the phrase "reduced instruction set computer" is the mistaken idea that instructions are simply eliminated, resulting in a smaller set of instructions. In fact, over the years, RISC instruction sets have grown in size, and today many of them have a larger set of instructions than many CISC CPUs. Some RISC processors such as the [[INMOS]] [[Transputer]] have instruction sets as large as, say, the CISC [[IBM]] [[System/370]]; and conversely, the DEC [[PDP-8]] – clearly a CISC CPU because many of its instructions involve multiple memory accesses – has only 8 basic instructions, plus a few extended instructions.

The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced – at most a single data memory cycle – compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction. In particular, RISC processors typically have separate instructions for I/O and data processing; as a consequence, industry observers have started using the terms "register-register" or "load-store" to describe RISC processors.

Some CPUs have been retroactively dubbed RISC — a Byte magazine article once referred to the [[6502]] as "the original RISC processor" due to its simplistic and nearly orthogonal instruction set (most instructions work with most addressing modes) as well as its 256 zero-page "registers". The 6502 is no load/store design however: arithmetic operations may read memory and instructions like INC and ROL even modify memory. Furthermore, orthogonality is equally often associated with "CISC". However, the 6502 may be regarded as similar to RISC (and early machines) in the fact that it uses no [[microcode]] sequencing. However, the well known fact that it employed longer but fewer clock cycles compared to many contemporary microprocessors was due to a more [[asynchronous]] design with less subdivision of internal machine cycles. This is similar to early machines, but not to RISC.

Some CPUs have been specifically designed to have a very small set of instructions – but these designs are very different from classic RISC designs, so they have been given other names such as [[minimal instruction set computer]] (MISC), [[Zero Instruction Set Computer]] (ZISC), [[one instruction set computer]] (OISC), [[transport triggered architecture]] (TTA), etc.

==Alternatives==
RISC was developed as an alternative to what is now known as [[Complex instruction set computer|CISC]].
Over the years, other strategies have been implemented as alternatives to RISC and CISC. Some examples are [[VLIW]], [[Minimal instruction set computer|MISC]], [[OISC]], [[massive parallel processing]], [[systolic array]], [[reconfigurable computing]], and [[dataflow architecture]].

==Typical characteristics of RISC==
For any given level of general performance, a RISC chip will typically have far fewer [[transistor]]s dedicated to the core logic which originally allowed designers to increase the size of the register set and increase internal parallelism.

Other features, which are typically found in RISC architectures are:

* Uniform instruction format, using a single word with the opcode in the same bit positions in every instruction, demanding less decoding;
* Identical [[general purpose registers]], allowing any register to be used in any context, simplifying compiler design (although normally there are separate [[floating point]] registers);
* Simple [[addressing mode]]s. Complex addressing performed via sequences of arithmetic and/or load-store operations;
* Few data types in hardware, some CISCs have [[byte]] [[string (computer science)|string]] instructions, or support [[complex number]]s; this is so far unlikely to be found on a RISC.

Exceptions abound, of course, within both CISC and RISC.

RISC designs are also more likely to feature a [[Harvard architecture|Harvard memory model]], where the instruction stream and the data stream are conceptually separated; this means that modifying the memory where code is held might not have any effect on the instructions executed by the processor (because the CPU has a separate instruction and data [[cache]]), at least until a special synchronization instruction is issued. On the upside, this allows both caches to be accessed simultaneously, which can often improve performance.

Many early RISC designs also shared the characteristic of having a [[branch delay slot]]. A branch delay slot is an instruction space immediately following a jump or branch. The instruction in this space is executed, whether or not the branch is taken (in other words the effect of the branch is delayed). This instruction keeps the [[arithmetic and logical unit|ALU]] of the CPU busy for the extra time normally needed to perform a branch. Nowadays the branch delay slot is considered an unfortunate side effect of a particular strategy for implementing some RISC designs, and modern RISC designs generally do away with it (such as [[PowerPC]], more recent versions of SPARC, and MIPS).

==Early RISC==

The first system that would today be known as RISC was the [[CDC 6600]] [[supercomputer]], designed in 1964, a decade before the term was invented. The CDC 6600 had a load-store architecture with only two [[addressing mode]]s (register+register, and register+immediate constant) and 74 opcodes (whereas an [[Intel 8086]] has 400). The 6600 had eleven pipelined functional units for arithmetic and logic, plus five load units and two store units; the memory had multiple banks so all load-store units could operate at the same time. The basic clock cycle/instruction issue rate was 10 times faster than the memory access time. Jim Thornton and [[Seymour Cray]] designed it as a number-crunching CPU supported by 10 simple computers called "peripheral processors" to handle I/O and other operating system functions. Thus the joking comment later that the acronym RISC actually stood for "'''R'''eally '''I'''nvented by '''S'''eymour '''C'''ray".

The earliest attempt to make a chip-based RISC CPU was a project at [[International Business Machines|IBM]] which started in 1975. Named after the building where the project ran, the work led to the [[IBM 801]] CPU family which was used widely inside IBM hardware. The 801 was eventually produced in a single-chip form as the [[ROMP]] in 1981, which stood for 'Research OPD [Office Products Division] Micro Processor'. As the name implies, this CPU was designed for "mini" tasks, and when IBM released the [[IBM RT-PC]] based on the design in 1986, the performance was not acceptable. Nevertheless the 801 inspired several research projects, including new ones at IBM that would eventually lead to their [[IBM POWER|POWER]] system.

The most public RISC designs, however, were the results of university research programs run with funding from the [[DARPA]] [[VLSI Project|VLSI Program]]. The VLSI Program, practically unknown today, led to a huge number of advances in chip design, fabrication, and even computer graphics.

[[University of California, Berkeley|UC Berkeley]]'s [[Berkeley RISC|RISC project]] started in 1980 under the direction of [[David A. Patterson (scientist)|David Patterson]] and [[Carlo H. Sequin]], based on gaining performance through the use of pipelining and an aggressive use of a technique known as [[register window]]ing. In a normal CPU one has a small number of registers, and a program can use any register at any time. In a CPU with [[register window]]s, there are a huge number of registers, e.g. 128, but programs can only use a small number of them, e.g. 8, at any one time.
A program that limits itself to 8 registers per procedure can make very fast procedure calls: The call simply moves the window "down" by 8, to the set of 8 registers used by that procedure, and the return moves the window back. (On a normal CPU, most calls must save at least a few registers' values to the stack in order to use those registers as working space, and restore their values on return.)

The RISC project delivered the RISC-I processor in 1982. Consisting of only 44,420 transistors (compared with averages of about 100,000 in newer CISC designs of the era) RISC-I had only 32 instructions, and yet completely outperformed any other single-chip design. They followed this up with the 40,760 transistor, 39 instruction RISC-II in 1983, which ran over three times as fast as RISC-I.

At about the same time, [[John L. Hennessy]] started a similar project called [[MIPS architecture|MIPS]] at [[Stanford University]] in 1981. MIPS focused almost entirely on the pipeline, making sure it could be run as "full" as possible. Although pipelining was already in use in other designs, several features of the MIPS chip made its pipeline far faster. The most important, and perhaps annoying, of these features was the demand that all instructions be able to complete in one cycle. This demand allowed the pipeline to be run at much higher data rates (there was no need for induced delays) and is responsible for much of the processor's performance. However, it also had the negative side effect of eliminating many potentially useful instructions, like a multiply or a divide.

In the early years, the RISC efforts were well known, but largely confined to the university labs that had created them. The Berkeley effort became so well known that it eventually became the name for the entire concept. Many in the computer industry criticized that the performance benefits were unlikely to translate into real-world settings due to the decreased memory efficiency of multiple instructions, and that that was the reason no one was using them. But starting in 1986, all of the RISC research projects started delivering products.

==Later RISC==

Berkeley's research was not directly commercialized, but the RISC-II design was used by [[Sun Microsystems]] to develop the [[SPARC]], by [[Pyramid Technology]] to develop their line of mid-range multi-processor machines, and by almost every other company a few years later. It was Sun's use of a RISC chip in their new machines that demonstrated that RISC's benefits were real, and their machines quickly outpaced the competition and essentially took over the entire [[workstation]] market.

John Hennessy left Stanford (temporarily) to commercialize the MIPS design, starting the company known as [[MIPS Computer Systems]]. Their first design was a second-generation MIPS chip known as the '''[[R2000 (microprocessor)|R2000]]'''. MIPS designs went on to become one of the most used RISC chips when they were included in the [[PlayStation]] and [[Nintendo 64]] [[game console]]s. Today they are one of the most common [[embedded processor]]s in use for high-end applications.

IBM learned from the RT-PC failure and went on to design the RS/6000 based on their new POWER architecture. They then moved their existing [[AS/400]] systems to POWER chips, and found much to their surprise that even the very complex instruction set ran considerably faster. POWER would also find itself moving "down" in scale to produce the [[PowerPC]] design, which eliminated many of the "IBM only" instructions and created a single-chip implementation. Today the [[PowerPC]] is one of the most commonly used CPUs for automotive applications (some cars have more than 10 of them inside). It was also the CPU used in most [[Apple Macintosh]] machines from 1994 to 2006. (Starting in February 2006, Apple [[Apple Intel transition|switched]] their main production line to [[Intel]] [[x86]] processors.)

Almost all other vendors quickly joined. From the [[United Kingdom|UK]] similar research efforts resulted in the [[INMOS transputer]], the [[Acorn Archimedes]] and the [[ARM Ltd|Advanced RISC Machine]] line, which is a huge success today. Companies with existing CISC designs also quickly joined the revolution. [[Intel]] released the [[Intel i860|i860]] and [[Intel i960|i960]] by the late 1980s, although they were not very successful. [[Motorola]] built a new design called the [[Motorola 88000|88000]] in homage to their famed CISC [[Motorola 68000|68000]], but it saw almost no use and they eventually abandoned it and joined IBM to produce the PowerPC. [[Advanced Micro Devices|AMD]] released their [[AMD 29000|29000]] which would go on to become the most popular RISC design of the early 1990s.

Today the vast majority of all 32-bit CPUs in use are RISC CPUs, and [[microcontroller]]s. RISC design techniques offers power in even small sizes, and thus has become dominant for low-power 32-bit CPUs. Embedded systems are by far the largest market for processors: while a family may own one or two PCs, their car(s), cell phones, and other devices may contain a total of dozens of embedded processors. RISC had also completely taken over the market for larger workstations for much of the 90s (until taken back by inexpensive PC-based solutions). After the release of the Sun SPARCstation the other vendors rushed to compete with RISC based solutions of their own. The high-end server market today is almost completely RISC based, and the #1 spot among [[supercomputer]]s is held by [[IBM]]'s [[Roadrunner (supercomputer)|Roadrunner]] system, which uses [[Power Architecture]]-based [[Cell (microprocessor)|Cell processors]]to provide most of its computing power, although many other supercomputers use [[x86]] [[Complex instruction set computer|CISC]] processors instead.

===RISC and x86===
However, despite many successes, RISC has made few inroads into the desktop PC and commodity server markets, where [[Intel]]'s [[x86]] platform remains the dominant processor architecture ([[Intel]] is facing increased competition from [[Advanced Micro Devices|AMD]], but even AMD's processors implement the [[x86]] platform, or a 64-bit superset known as [[x86-64]]). There are three main reasons for this.
# The very large base of [[proprietary software|proprietary]] PC applications are written for x86, whereas no RISC platform has a similar installed base, and this meant PC users were [[vendor lock-in|locked into]] the x86.
# Although RISC was indeed able to scale up in performance quite quickly and cheaply, Intel took advantage of its large market by spending vast amounts of money on processor development. Intel could spend many times as much as any RISC manufacturer on improving low level design and manufacturing. The same could not be said about smaller firms like [[Cyrix]] and [[NexGen]], but they realized that they could apply pipelined design philosophies and practices to the x86-architecture — either ''directly'' as in the 6x86 and MII series, or ''indirectly'' (via extra decoding stages) as in [[Nx586]] and [[AMD K5]].
# Later, more powerful processors such as [[Intel P6]] and [[AMD K6]] had similar RISC-like units that executed a stream of [[micro-operation]]s generated from decoding stages that split most x86 instructions into several pieces. Today, these principles have been further refined and are used by modern x86 processors such as [[Intel Core 2]] and [[AMD K8]]. The first ''available'' chip deploying such techniques was the NexGen Nx586, released in 1994 (while the AMD K5 was severely delayed and released in 1995).

While early RISC designs were significantly different than contemporary CISC designs, by 2000 the highest performing CPUs in the RISC line were almost indistinguishable from the highest performing CPUs in the CISC line.

A number of vendors, including [[Qualcomm]], are attempting to enter the PC market with [[ARM architecture|ARM-based]] devices dubbed [[smartbook]]s, riding off the [[netbook]] trend and rising acceptance of [[Linux distribution]]s, a number of which already have ARM builds.
Other companies are choosing to use [[Windows CE]].

===Diminishing benefits===
Over time, improvements in chip fabrication techniques have improved performance exponentially, according to [[Moore's law]], whereas architectural improvements have been comparatively small. Modern CISC implementations have implemented many of the performance improvements introduced by RISC, such as single-clock throughput of simple instructions. Compilers have also become more sophisticated, and are better able to exploit complex as well as simple instructions on CISC architectures, often carefully optimizing both instruction selection and instruction and data ordering in pipelines and caches. The RISC-CISC distinction has blurred significantly in practice.

===RISC success stories===

RISC designs have led to a number of successful platforms and architectures, some of the larger ones being:

*[[ARM architecture|ARM]] — The ARM architecture dominates the market for low power and low cost embedded systems (typically 100–500 MHz in 2008). ARM Ltd., which licenses intellectual property rather than manufacturing chips, reported that 10 billion licensed chips had been shipped as of early 2008. The various generations, variants and implementations of the ARM core are deployed in over 90% of mobile electronics devices, including almost all modern mobile phones, mp3 players and portable video players. Some high profile examples are
**Apple [[iPod]]s (custom [[ARM7TDMI]] SoC)
**Apple [[iPhone]] and [[iPod Touch]] (Samsung [[ARM11|ARM1176JZF]], [[ARM Cortex-A8]])
**Palm and PocketPC PDAs and smartphones (Marvell [[XScale]] family, Samsung SC32442 - ARM9)
**[[RIM]] [[Blackberry]] smartphone/email devices.
**Microsoft [[Windows Mobile]]
**Nintendo [[Game Boy Advance]] (ARM7TDMI)
**[[Nintendo DS]] (ARM7TDMI, ARM946E-S)
**Sony Network Walkman (Sony in-house ARM based chip)
**T-Mobile G1 (HTC Dream Android, Qualcomm MSM7201A [[ARM11]] @ 528MHz)
*[[PowerPC]] Architecture - The PowerPC architecture is a popular RISC based architecture that dominates the performance and power constraint embedded device markets such as communication equipments (Routers, Switches), storage equipments etc.
*MIPS's [[MIPS architecture|MIPS]] line, found in most [[Silicon Graphics|SGI]] computers and the [[PlayStation]], [[PlayStation 2]], [[Nintendo 64]] (discontinued), [[PlayStation Portable]] game consoles, and [[residential gateway]]s like [[Linksys WRT54G series]].
*[[IBM]]'s and [[Freescale]]'s (formerly [[Motorola]] SPS) [[Power Architecture]], used in all of IBM's supercomputers, midrange servers and workstations, in [[Apple Inc.|Apple]]'s [[PowerPC]]-based [[Macintosh]] computers (discontinued), in [[Nintendo]]'s [[Nintendo Gamecube|Gamecube]] and [[Wii]], [[Microsoft]]'s [[Xbox 360]] and [[Sony]]'s [[PlayStation 3]] game consoles, [[EMC Corporation|EMC]]'s DMX range of the [[Symmetrix]] [[Storage area network|SAN]], and in many embedded applications like printers and cars.
*[[Sun Microsystems|Sun]]'s [[SPARC]] line, found in most of their later machines
*[[Hewlett-Packard]]'s [[PA-RISC]], also known as HP-PA, discontinued December 31, 2008.
*[[DEC Alpha|Alpha]], used in single-board computers, workstations, servers and supercomputers from [[Digital Equipment Corporation]], [[Compaq]] and [[HP]], discontinued as of 2007.
*[[XAP processor]] used in many low-power wireless ([[Bluetooth]], [[wifi]]) chips from [[CSR plc|CSR]].
*[[Hitachi, Ltd.|Hitachi]]'s [[SuperH]], originally in wide use in the [[Sega]] [[Sega 32X|Super 32X]], [[Sega Saturn|Saturn]] and [[Dreamcast]], now at the heart of many consumer electronics devices. The SuperH is the base platform for the [[Mitsubishi]] - [[Hitachi, Ltd.|Hitachi]] joint semiconductor group. The two groups merged in 2002, dropping Mitsubishi's own RISC architecture, the [[M32R]].
*[[Atmel AVR]] used in a variety of products including ranging from Xbox handheld controllers to BMW cars.

==See also==
*[[Addressing mode]]
*[[Complex instruction set computer]]
*[[Very long instruction word]]
*[[Minimal instruction set computer]]
*[[Zero Instruction Set Computer]]
*[[One instruction set computer]]
*[[NISC]] (No-instruction-set-computer)
*[[Ultimate RISC]]
*[[Microprocessor]]
*[[Instruction set]]
*[[Computer architecture]]
*[[Classic RISC pipeline]]

==External links==
*[http://cse.stanford.edu/class/sophomore-college/projects-00/risc/risccisc/ RISC vs. CISC]
*[http://cse.stanford.edu/class/sophomore-college/projects-00/risc/whatis/index.html What is RISC]
*[http://www.cpushack.net/CPU/cpuAppendA.html RISC vs. CISC from historical perspective]

Reduced Instruction Set Computer - Revision history

Onnowpurbo: New page: The acronym '''RISC''' (pronounced as ''risk''), for '''reduced instruction set computer''', represents a CPU design strategy emphasizing the insight that simplifie...